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k) The host shall negate STOP and assert – HDMARDY within t ENV after asserting – DMACK. After negating STOP
and asserting – HDMARDY, the host shall not change the state of either signal until after receiving the first
transition of DSTROBE from the device (i.e., after the first data word has been received).
l)
The device shall drive D[15:00] no sooner than t ZAD after the host has asserted – DMACK, negated STOP, and
asserted – HDMARDY.
m) The device shall drive the first word of the data transfer onto D[15:00]. This step may occur when the
device first drives D[15:00] in step (j).
n) To transfer the first word of data the device shall negate DSTROBE within t FS after the host has negated
STOP and asserted – HDMARDY. The device shall negate DSTROBE no sooner than t DVS after driving the first
word of data onto D[15:00].
Figure 10: Ultra DMA Data-In Burst Initiation Timing
Notes: The definitions for the IORDY:-DDMARDY:DSTROBE, -IORD: -HDMARDY:HSTROBE, and – IOWR:STOP signal lines
are not in effect until DMARQ and – DMACK are asserted.
6.5.4.4.2 Sustaining an Ultra DMA Data-In Burst
An Ultra DMA Data-In burst is sustained by following the steps lettered below. The timing diagram is shown in
Figure 11: Sustained Ultra DMA Data-In Burst Timing. The timing parameters are specified in Table 27: Ultra DMA
Data Burst Timing Requirements and are described in Table 28: Ultra DMA Data Burst Timing Descriptions.
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.20
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
C-320_data_sheet_CF-HxBO_Rev120.doc
Page 31 of 101
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